New Efficient 4-bit Asynchronous Counter

Designing logical circuits with lower hardware implementation is an important issue which is mentioned nowadays. Lower hardware implementation can causes better layout area, switching delay and power consumption. In this paper a novel efficient counter architecture is presented. This component is suitable for designing semiconductor transistor based circuits. A new 4-bit counter is designed which is expandable and is modeled by VHDL. The proposed architecture includes 27 transistors and caused 27 transistors improvement. The proper functionality of the counter is checked by means of computer simulation using ModelSim tool