• DocumentCode
    1000577
  • Title

    Integrating an Electron-Beam System into VLSI Fault Diagnosis

  • Author

    Tamama, Teruo ; Kuji, Norio

  • Author_Institution
    NTT Electrical Communications Laboratories
  • Volume
    3
  • Issue
    4
  • fYear
    1986
  • Firstpage
    23
  • Lastpage
    29
  • Abstract
    Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connections in different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beam tester. The system has successfully tested a 75K-transistor VLSI device.
  • Keywords
    Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Design automation; Fault diagnosis; Integrated circuit interconnections; System testing; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1986.294966
  • Filename
    4069824
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1000577