• DocumentCode
    1000673
  • Title

    SMART And FAST: Test Generation for VLSI Scan-Design Circuits

  • Author

    Abramovici, M. ; Kulikowski, J.J. ; Menon, P.R. ; Miller, D.T.

  • Author_Institution
    AT&T Information Systems
  • Volume
    3
  • Issue
    4
  • fYear
    1986
  • Firstpage
    43
  • Lastpage
    54
  • Abstract
    This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithms include: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm for dynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whose objective is to minimize the amount of search done in test generation.
  • Keywords
    Automatic testing; Central Processing Unit; Circuit faults; Circuit testing; Clocks; Logic; Master-slave; Sequential analysis; System testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1986.294975
  • Filename
    4069833
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1000673