Title :
Chip area estimation method for VLSI chip floor plan
Author :
Kitazawa, Hiroyasu ; Ueda, Kazunori
Author_Institution :
NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan
Abstract :
A chip area estimation method is presented, which consists of intrablock area calculation based on empirically obtained block data and interblock channel area calculation. The method is used in a chip floor program for hierarchical standard-cell VLSI layout design. By applying to several practical circuits, it is shown that the estimation error is within ±10%.
Keywords :
circuit layout CAD; estimation theory; integrated circuit technology; large scale integration; CAD; IC technology; VLSI; chip area estimation method; chip floor program; computer-aided design; hierarchical standard-cell; intrablock area calculation; layout design;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840093
