DocumentCode :
1001382
Title :
A novel systolic array structure for DCT
Author :
Cheng, Chao ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Volume :
52
Issue :
7
fYear :
2005
fDate :
7/1/2005 12:00:00 AM
Firstpage :
366
Lastpage :
369
Abstract :
This paper presents a new algorithm for the implementation of discrete cosine transform (DCT), based on the idea of reformulating prime N-length DCT into two cyclic convolutions with exactly the same structure, which are implemented with a proposed fast cyclic convolution-based systolic array structure. The proposed algorithm can save (N-1)/2 multiplications and 2Nregisters, at the cost of only (N-1)/2 additions of those used in previous designs. The I/O is kept low because of the simple control complexity of the algorithm. Furthermore, this new algorithm preserves all the other benefits of very large-scale integration algorithms based on circular correlation or cyclic convolution, such as regular and simple structure.
Keywords :
VLSI; computational complexity; convolution; digital arithmetic; discrete cosine transforms; multiplying circuits; systolic arrays; discrete cosine transform; fast cyclic convolution; prime N-length DCT; systolic array structure; very large-scale integration algorithms; Chaos; Convolution; Costs; Discrete cosine transforms; Equations; Hardware; Large scale integration; Systolic arrays; Throughput; Very large scale integration; Discrete cosine transform (DCT); fast convolution; systolic array; very large-scale integration (VLSI) implementation;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2005.850432
Filename :
1468332
Link To Document :
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