Post-irradiation effects in CMOS integrated circuits [SRAMs]

The postirradiation response of CMOS integrated circuits from three vendors was measured as a function of temperature and irradiation bias. It was found that a worst-case anneal temperature for rebound testing is highly process-dependent. At an anneal temperature of 80°C, the timing parameters of a 16 K SRAM from vendor A quickly saturate at maximum values and display no further changes at this temperature. At higher temperatures, evidence for the anneal of the interface-state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is no longer. CMOS/SOS integrated circuits (vendor B) showed similar behavior, except that the saturation value for the timing parameters was stable up to 105°C. After irradiation to 10 Mrad(Si), a 16 K SRAM (vendor C) was annealed at 80°C, and the access time decreased toward prerad values during the anneal