• DocumentCode
    1001581
  • Title

    A novel dual p-/p+ poly gate CMOS VLSI technology

  • Author

    Pfiester, James R. ; Parrillo, Louis C.

  • Author_Institution
    Motorola Adv. Products Res. & Dev. Lab., Austin, TX, USA
  • Volume
    35
  • Issue
    8
  • fYear
    1988
  • fDate
    8/1/1988 12:00:00 AM
  • Firstpage
    1305
  • Lastpage
    1310
  • Abstract
    A CMOS VLSI technology using p- and p+ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p - poly gate is shown to be compatible with p+ poly-gated surface-channel PMOS devices
  • Keywords
    CMOS integrated circuits; VLSI; integrated circuit technology; CMOS VLSI technology; NMOS transistor; PMOS transistor; improved field-effect mobility; p+ poly gates; p- poly gate; polycrystalline Si gates; surface-channel device; threshold voltage; Annealing; CMOS technology; Implants; MOS devices; MOSFETs; Protection; Resists; Silicon; Threshold voltage; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.2552
  • Filename
    2552
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1001581