Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64 K×1 NMOS SRAMs

Long time constants associated with extremely high pull-up resistances commonly used in high-density, polysilicon-load NMOS SRAMs were identified as the primary cause of single-event-induced, multiple-bit upsets recently observed in cyclotron tests. Diffusion currents can cause single-event errors in this long-time-constant regime. Above certain threshold linear energy transfers, multiple-bit upsets constitute almost all the single-event errors in the SRAMs. Conventionally calculated error cross-sections can be larger than the chip area and can result in unreasonably large bit error rates. A new method of defining the SEU figure-of-merit in space environments that includes multiple-bit upsets is needed