• DocumentCode
    1001591
  • Title

    Parallel processing of logic module placement

  • Author

    Sugiyama, Y. ; Watanabe, T.

  • Author_Institution
    NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan
  • Volume
    20
  • Issue
    5
  • fYear
    1984
  • Firstpage
    219
  • Lastpage
    220
  • Abstract
    A parallel-processing algorithm for logic module placement is presented. A pairwise interchange algorithm, directed by the steepest-descent concept, is expanded to the parallel-processing case. By using an AAP (adaptive array processor), it is shown that an N-module placement problem can be processed in 0.06N of the time required by a sequential computer (1 MIPS).
  • Keywords
    circuit layout CAD; logic CAD; modules; parallel processing; AAP; N-module placement problem; PCB layout; adaptive array processor; computing time; logic module placement; monolithic chip layout; pairwise interchange algorithm; parallel-processing algorithm; steepest-descent concept; time required;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19840145
  • Filename
    4249758
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1001591