Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors

Side-channel attacks threaten the security of any electronic device. We have developed a comprehensive back-end design flow that natively protects constant-power cryptoprocessors against side-channel attacks that exploit instant power consumption. The proposed methodology uses a fully custom, balanced cell library and an innovative place-and-route method. All the design steps in this methodology take place at the layout level. We apply the described flow to the quasi-delay-insensitive (QDI) SecLib library with a shielded routing method derived from back-end duplication, using legacy CAD tools for the back-end steps. In this article, we investigate the feasibility of implementing optimally secured unmasked logic. We argue that it is possible to thwart all known power attacks, at least on carefully designed netlist schematics.