Title :
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Author :
Guilley, Sylvain ; Flament, Florent ; Hoogvorst, Philippe ; Pacalet, Renaud ; Mathieu, Yves
Author_Institution :
Ecole Nat. Superieure des Telecommun., Paris
Abstract :
Side-channel attacks threaten the security of any electronic device. We have developed a comprehensive back-end design flow that natively protects constant-power cryptoprocessors against side-channel attacks that exploit instant power consumption. The proposed methodology uses a fully custom, balanced cell library and an innovative place-and-route method. All the design steps in this methodology take place at the layout level. We apply the described flow to the quasi-delay-insensitive (QDI) SecLib library with a shielded routing method derived from back-end duplication, using legacy CAD tools for the back-end steps. In this article, we investigate the feasibility of implementing optimally secured unmasked logic. We argue that it is possible to thwart all known power attacks, at least on carefully designed netlist schematics.
Keywords :
cryptography; logic CAD; microprocessor chips; cell library; electronic device security; legacy CAD tools; netlist schematics design; power-analysis- resistant cryptoprocessors; quasi delay-insensitive SecLib library; secured CAD back-end flow; secured unmasked logic; shielded routing method; side-channel attacks; CMOS logic circuits; Cryptography; Design automation; Field programmable gate arrays; Libraries; Logic design; Logic devices; Logic testing; Reconfigurable logic; Security; DFM; DFY; back-end design automation; mitigation; power-constant architectures; robust hardware; side-channel attacks;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2007.202
