DocumentCode
1002471
Title
An Introduction to Switch-Level Modeling
Author
Hayes, John P.
Author_Institution
University of Michigan
Volume
4
Issue
4
fYear
1987
Firstpage
18
Lastpage
25
Abstract
Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level, important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switch states, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structural information than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.
Keywords
Bipolar transistors; Capacitance; Design methodology; Digital circuits; Digital relays; Logic circuits; Logic gates; Switches; Switching circuits; Very large scale integration;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.1987.295145
Filename
4070015
Link To Document