• DocumentCode
    1002601
  • Title

    A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

  • Author

    Hirano, Yuuichi ; Tsujiuchi, Mikio ; Maki, Yukio ; Iwamatsu, Toshiaki ; Ishii, Yuichiro ; Miyanishi, Atsushi ; Tsukamoto, Yasumasa ; Nii, Koji ; Ipposhi, Takashi ; Oda, Hidekazu ; Maegawa, Shigeto ; Inoue, Yasuo

  • Author_Institution
    Renesas Technol. Corp., Itami
  • Volume
    55
  • Issue
    1
  • fYear
    2008
  • Firstpage
    365
  • Lastpage
    371
  • Abstract
    An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.
  • Keywords
    SRAM chips; driver circuits; low-power electronics; semiconductor device testing; silicon-on-insulator; actively body-bias controlled technology; driver transistors; forward biases; high-speed operation; low-voltage operation; neutron-accelerated soft-error testing; parasitic gate capacitance; silicon-on-insulator; static random access memory; word-line voltage; Driver circuits; Isolation technology; Joining processes; Low voltage; MOSFETs; Parasitic capacitance; Random access memory; SRAM chips; Silicon on insulator technology; Testing; Access time; body bias; multicell errors; neutron; silicon-on-insulator (SOI); soft error rate (SER); soft errors; static random access memory (SRAM); system on a chip (SoC); variation;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.910566
  • Filename
    4399664