• DocumentCode
    1003459
  • Title

    A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme

  • Author

    Ferriss, Mark A. ; Flynn, Michael P.

  • Author_Institution
    Michigan Univ., Ann Arbor, MI
  • Volume
    43
  • Issue
    11
  • fYear
    2008
  • Firstpage
    2464
  • Lastpage
    2471
  • Abstract
    In this work an all-digital phase detector for a fractional-N PLL is proposed and demonstrated. The phase detector consists of a single flip-flop, which acts as an oversampled 1 bit phase quantizer. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated, without compromising on the frequency accuracy of the output signal. A prototype 2.2 GHz fractional-N synthesizer incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142 kHz, an FSK modulation rate of 927.5 kbs is achieved. The 0.7 mm2 prototype is implemented in 0.13 mum CMOS consumes 14 mW from a 1.4 V supply.
  • Keywords
    CMOS digital integrated circuits; UHF integrated circuits; flip-flops; frequency shift keying; phase detectors; phase locked loops; quantisation (signal); signal sampling; FSK modulation rate; bandwidth 142 kHz; digital phase detector; digital sampling scheme; flip-flop; fractional-N PLL modulator; frequency 2.2 GHz; frequency switching scheme; mixed-mode CMOS; phase quantizer; power 14 mW; size 0.13 mum; voltage 1.4 V; Bandwidth; Detectors; Digital modulation; Flip-flops; Frequency shift keying; Phase detection; Phase locked loops; Prototypes; Sampling methods; Synthesizers; ADC; DAC; FSK; PML; delta-sigma; fractional-${N}$; fractional-PLL (FPLL); phase minimization loop; phase-locked loop (PLL); synthesizer;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2008.2005435
  • Filename
    4685428