Title :
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS
Author :
Mochizuki, Seiji ; Shibayama, Tetsuya ; Hase, Masaru ; Izuhara, Fumitaka ; Akie, Kazushi ; Nobori, Masaki ; Imaoka, Ren ; Ueda, Hiroshi ; Ishikawa, Kazuyuki ; Watanabe, Hiromi
Author_Institution :
Renesas Technol. Corp., Tokyo
Abstract :
We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder ldquoJM (Joint Model)rdquo.
Keywords :
CMOS digital integrated circuits; high definition video; low-power electronics; video codecs; video coding; H.264 reference encoder; H.264/MPEG-4 video codec IP; HD encoding; HD mobile applications; HD-sized moving pictures; digital still cameras; digital video cameras; encoding algorithms; frequency 144 MHz; frequency 54 MHz; macroblock-level pipeline method; mobile phones; power 64 mW; size 90 nm; Digital cameras; Digital recording; Encoding; Energy consumption; High definition video; MPEG 4 Standard; Motion control; Motion estimation; Pipelines; Video codecs; Clock gating; H.264 video codec; MPEG-4 video codec; high picture quality; low power consumption; mobile application;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2004534
