DocumentCode :
1003734
Title :
Shared row multiplier
Author :
Moreno, Juan Manuel ; Castillo, Felipe ; Cabestany, J.
Author_Institution :
Univ. Politecnica de Catalunya, Barcelona, Spain
Volume :
28
Issue :
15
fYear :
1992
fDate :
7/16/1992 12:00:00 AM
Firstpage :
1463
Lastpage :
1465
Abstract :
A new digital multiplication structure, called the shared row multiplier, is presented. This multiplier can be easily implemented in silicon, and achieves a good execution time-occupied area product. The multiplier is derived by converting the usual spatial information flow of the multiplication into a temporal flow, thus reducing the number of cells (occupied area) required for completing the whole multiplication algorithm.
Keywords :
cellular arrays; digital arithmetic; logic arrays; multiplying circuits; digital multiplication structure; shared row multiplier;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19920931
Filename :
256076
Link To Document :
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