Title :
Systolic encoder for fast waveform vector quantisation
Author :
Wang Chin-Liang ; Wei Che-Ho ; Chen Sin-Horng
Author_Institution :
National Chiao Tung University, Institute of Electronics, Hsin-Chu, Republic of China
Abstract :
The letter presents a systolic architecture that can efficiently perform the encoding operations of waveform vector quantisation using the squared-error distortion measure. In the system, squared-error cells and comparing cells are used to achieve modularity and concurrency. An index offset approach is employed for reducing I/O pins.
Keywords :
analogue-digital conversion; encoding; comparing cells; concurrency; encoding operations; fast waveform vector quantisation; index offset approach; modularity; reducing I/O pins; squared-error cells; squared-error distortion measure; systolic architecture; systolic encoder;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19850483
