Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

Precise behavioral modeling of switched-capacitor ΔΣ modulators is presented. Considering noise (switches´ and op-amps´ thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches´ clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many ΔΣ modulators´ modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators´ behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-μm CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment.