Title :
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
Author :
Chuang, Chi-Nan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.
Keywords :
CMOS integrated circuits; delay lock loops; jitter; timing circuits; CMOS process; cycle jitter calibration; delay-locked loop; duty cycle correction circuit; edge combiner; frequency 3 GHz to 8 GHz; peak-to-peak jitters; voltage-controlled delay line; Calibration; cycle jitter; delay-locked loop (DLL); duty cycle correction; edge combiner;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2008.2002561
