Implementation of a flattening image method by inverse transformation, using different resources

This work is referred to an image flattening method using inverse transformation. Are proposed and analyzed several implementation trough the use of different resources of software and hardware. Programmable Logical Devices as FPGA are used to obtain that the processing of the algorithm outlined can be done in real time, in such a way that allows to solve critical performance constraint in production lines. The FPGA in which this work was probed is a 2000E Virtex from Xilinx. This PLD is mounted in a RC1000 board from Celoxica, which can be used in a PC trough the PCI bus. Finally are shown the time reached for the different alternatives proposed, obtaining values that make possible an application in real time.