• DocumentCode
    1004742
  • Title

    Computer simulation of an oxide walled emitter STL gate

  • Author

    Roulston, D.J. ; Depey, M.

  • Author_Institution
    University of Waterloo, Electrical Engineering Department, Waterloo, Canada
  • Volume
    19
  • Issue
    1
  • fYear
    1983
  • Firstpage
    21
  • Lastpage
    22
  • Abstract
    A Schottky transistor logic (STL) gate is studied using computer simulation. The relation between propagation delay time and the spacing between the diffused emitter and the isolation oxide is shown to be such that an optimum spacing exists.
  • Keywords
    bipolar integrated circuits; digital simulation; integrated logic circuits; logic gates; STL gate; Schottky transistor logic; computer simulation; diffused emitter; isolation oxide; propagation delay;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19830015
  • Filename
    4250769
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1004742