A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers

Author

Krishnaswamy, Harish ; Hashemi, Hossein

Volume

43

Issue

11

fYear

2008

Firstpage

2446

Lastpage

2463

Abstract

A variable-phase ring oscillator (VPRO) and phase-locked loop (PLL) architecture is introduced for integrated phased arrays. The architecture eliminates key building blocks such as mixers, phase shifters and power splitters/combiners, allowing for compact and low-power implementations. This paper presents the principles of operation of the architecture in transmit and receive modes, along with a detailed theoretical treatment of critical performance metrics such as linearity and sensitivity. In addition, measured results from a prototype, 24 GHz , 4-channel, phased-array transceiver, implemented in a 0.13 mum CMOS process, are presented.

Keywords

CMOS integrated circuits; low-power electronics; microwave integrated circuits; microwave oscillators; phase locked loops; transceivers; CMOS process; PLL architecture; critical performance metrics; frequency 24 GHz; integrated phased array transceivers; linearity; low-power implementations; phase-locked loop; receiver modes; sensitivity; size 0.13 mum; transmitting mode; variable-phase ring oscillator; CMOS process; Delay; Linearity; Phase locked loops; Phase measurement; Phase shifters; Phased arrays; Prototypes; Ring oscillators; Transceivers; Phase locked loops (PLLs); phase noise; phase shifters; phased arrays; sensitivity; transceivers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.2005445

Filename

4685986