• DocumentCode
    1008642
  • Title

    Novel switched logic CMOS latch building block

  • Author

    Spaanenburg, L. ; Pollok, W. ; Vermeulen, W.

  • Author_Institution
    Twente University of Technology, Department of Electronic Engineering, Enschede, Netherlands
  • Volume
    21
  • Issue
    9
  • fYear
    1985
  • Firstpage
    398
  • Lastpage
    399
  • Abstract
    A six-transistor static CMOS building block for latches is proposed, based on the use of PMOS and NMOS switches. It is shown how latches can be built from this building block.
  • Keywords
    CMOS integrated circuits; integrated logic circuits; logic design; D-latch; NMOS switches; PMOS switches; building block; logic IC; logic design; six transistor configuration; switched logic CMOS latch;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19850283
  • Filename
    4251184
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1008642