Title :
Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning
Author :
Wang, Hua ; Miranda, Miguel ; Dehaene, Wim ; Catthoor, Francky
Author_Institution :
IMEC, Katholieke Univ. Leuven, Leuven
Abstract :
This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal energy-delay (E/D) tradeoffs via the buffer gate sizes and adding supply voltage as an extra tuning knob. In addition, a detailed discussion of the practically achievable tradeoff ranges via the gate size and especially supply voltage tuning is present. We have applied the methodology for the design and fine tuning of the run-time switchable buffers within the Level-1 (L1) embedded SRAMs (eSRAM), confirming that a very wide range in delay and energy reduction (up to 50%) can be achieved when compared to solely optimal speed eSRAM design using conventional high speed buffers.
Keywords :
CMOS digital integrated circuits; Pareto optimisation; SRAM chips; buffer storage; circuit tuning; embedded systems; integrated circuit design; CMOS devices; Pareto buffer design; Pareto optimal energy-delay tradeoffs; buffer gate size; extra tuning knob; optimal speed embedded SRAM design; run-time switchable buffers; supply voltage tuning; variable tapered buffer chains; CMOS buffer; low power design; supply voltage scaling; tradeoffs;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2003169
