Title :
First level calorimeter trigger system for the Large Hadron Collider
Author :
Eisenhandler, E. ; Gee, N. ; Gillman, A. ; Perera, V. ; Quinton, S. ; Ellis, N. ; Fensome, I. ; Garvey, J. ; Jovanovic, P. ; Staley, R. ; Watson, A.
Author_Institution :
Queen Mary & Westfield Coll., London Univ., UK
fDate :
8/1/1993 12:00:00 AM
Abstract :
As part of a research and development project to study first-level calorimeter triggers for the Large Hadron Collider (LHC) an application specific integrated circuit (ASIC) is designed. It will search for candidate electromagnetic clusters associated with a particular cell from a 4×4 area of the calorimeter. The ASIC takes in sixteen (4×4) 8-b digitized signals from the calorimeter and will provide two results: (i) a flag to indicate the presence of an EM cluster; and (ii) a sum over the 4×4 area which will be used in the subsequent logic in the trigger system to search for jets and to calculate missing transverse energy. In the LHC, the bunch-crossing period is 15 ns, and therefore the logic is implemented on the ASIC using a pipelined architecture, with pipeline steps of 15 ns. The algorithm is implemented on a 0.8-μm CMOS gate array and is packaged in a 179 pin ceramic pin grid array. The ASIC is tested above the full operating frequency of 67 MHz
Keywords :
application specific integrated circuits; nuclear electronics; proton accelerators; storage rings; synchrotrons; trigger circuits; 67 MHz; ASIC; CMOS gate array; LHC; Large Hadron Collider; application specific integrated circuit; bunch-crossing period; ceramic pin grid array; electromagnetic clusters; first-level calorimeter triggers; jets; missing transverse energy; pipelined architecture; Application specific integrated circuits; CMOS logic circuits; Clocks; Clustering algorithms; Educational institutions; Electrons; Laboratories; Large Hadron Collider; Pipelines; Research and development;
Journal_Title :
Nuclear Science, IEEE Transactions on
