Phase-shifter thinning and sidelobe reduction for large phased arrays

Thinning of phase shifters (the deletion of some individual phase shifters and the use of common ones to adjust the phase of more than one element) in a large phased array is a means for reducing circuit complexity and system cost. This practice gives rise to phase errors which cause a deterioration in the array pattern. One of the most objectionable results is an excessive rise in some of the sidelobes whose locations and magnitudes depend on the direction of scan and other array parameters. This paper introduces a method for determining the region and the extent of pattern deterioration when each phase shifter is used to control the phase of two elements in a linear array. A procedure based on the steepest-descent technique for an optimum reduction in the high sidelobes by breaking the regularity of the phase errors is also presented. The procedure is independent of the total number of array elements. Numerical examples are given.