An integrated high performance FASTBUS slave interface

A high-performance CMOS FASTBUS slave interface ASIC (application specific integrated circuit) supporting all addressing and data transfer modes defined in the IEEE 960-1986 standard is presented. The FASTBUS slave integrated circuit (FASIC) is an interface between the synchronous FASTBUS and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32-b microprocessor. The FASIC is a programmable device, which makes possible its direct use in many different applications. A set of programmable address mapping windows can map FASTBUS addresses to convenient memory addresses and, at the same time, act as address decoding logic. Data rates of 100 Mbyte/s to FASTBUS can be obtained using an internal first-in first-out (FIFO) in the FASIC to buffer data between the two buses during block transfers. Message passing from FASTBUS, to a microprocessor on the slave module is supported. A compact (70-mm×170-mm) FASTBUS slave piggyback subcard interface, including level conversion between emitter-coupled logic (ECL) and transistor-transistor logic (TTL) signal levels, is implemented using surface mount components and the 208-pin FASIC chip