Fabrication of a miniaturized DCL OR gate

Using niobium edge junctions and electron beam lithography (EBL) we have made direct coupled logic (DCL) OR gates with 1 μm minimum line widths. The gate cell, containing an isolator and a buffer section, fits into an area of approximately 25 by 30 μm². Our computer simulations show that these gates can have switching times of less than 10 ps. We have simulated the DCL circuit with several values of the most space-consuming element, an inductor. This paper describes the results of these simulations and presents a detailed description of the 7-level fabrication process. The mix of optical and electron-beam lithography used relies heavily on an inexpensive, yet powerful, circuit layout program.