DocumentCode
1010495
Title
Assessing RJSCs In High-Level Language Support
Author
Patterson, David A. ; Piepho, Richard S.
Author_Institution
University of California, Berkeley
Volume
2
Issue
4
fYear
1982
Firstpage
9
Lastpage
19
Abstract
A reduced instruction set computer, RISC I, was compared to five traditional machines. It provided the highest performance with the smallest penalty for using high-level language.
Keywords
Assembly systems; Computer aided instruction; Computer architecture; Computer errors; Delay effects; Design optimization; High level languages; Reduced instruction set computing; Registers; Springs;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.1982.291014
Filename
4070839
Link To Document