Title :
Assessing RJSCs In High-Level Language Support
Author :
Patterson, David A. ; Piepho, Richard S.
Author_Institution :
University of California, Berkeley
Abstract :
A reduced instruction set computer, RISC I, was compared to five traditional machines. It provided the highest performance with the smallest penalty for using high-level language.
Keywords :
Assembly systems; Computer aided instruction; Computer architecture; Computer errors; Delay effects; Design optimization; High level languages; Reduced instruction set computing; Registers; Springs;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.1982.291014
