DocumentCode
1011009
Title
6.1 GHz 4.6 mW CMOS divide-by-55/56 prescaler
Author
Yu, Xiao Peng ; Lim, Wei Meng ; Do, M.A. ; Yan, X.L. ; Yeo, Kiat Seng
Author_Institution
Inst. of VLSI Design, Zhejiang Univ., Hangzhou
Volume
44
Issue
24
fYear
2008
Firstpage
1402
Lastpage
1403
Abstract
A divide-by-55/56 phase switching prescaler based on odd phase signals is proposed. The odd phase signals for phase switching are generated by a divide-by-7 injection-locked frequency divider. A simple topology with a high operating frequency and a low power consumption is obtained. Implemented with a standard 0.18 m CMOS process, the prescaler is able to work from 3.2 to 6.1 GHz with a maximum measured power consumption of 4.6 mW from a 1.8 V supply voltage.
Keywords
CMOS logic circuits; frequency dividers; high-speed integrated circuits; low-power electronics; network topology; power consumption; prescalers; programmable circuits; CMOS process; divide -by-7 injection-locked frequency divider; divide-by-55/56 phase switching prescaler; frequency 3.2 GHz to 6.1 GHz; high-speed programmable frequency divider; odd phase signals; power 4.6 mW; power consumption; topology; voltage 1.8 V; wireless communications;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20081871
Filename
4689484
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