DocumentCode :
1011033
Title :
The v2.0+EDR Bluetooth SOC architecture for multimedia
Author :
Kim, Jeonghun ; Choi, Youngwhan ; Jeong, Jungwon ; Lee, Suhho ; Kim, Suki
Author_Institution :
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
Volume :
52
Issue :
2
fYear :
2006
fDate :
5/1/2006 12:00:00 AM
Firstpage :
436
Lastpage :
444
Abstract :
This paper presents a Bluetooth system on chip (SOC) architecture for multimedia applications. The SOC includes all necessary baseband-parts, RF-parts, a sub-band codec (SBC) and an application processor to achieve a Bluetooth specification v2.0+EDR (enhanced data rate). Dual bus architecture is selected to improve data transmission efficiency between a baseband and a system bus. The receiver uses an optimized low-IF (1.5 MHz) architecture which is trade-off between power and performance on CMOS technology. The transmitter uses a direct up conversion architecture. This chip occupies a die size of 28 mm2 in a 0.18 μm CMOS. This chip and a flash memory are put into multi chip package (MCP). The maximum current consumption of the total chip is 65 mA at the TX mode. The internal supply voltages of RF- and digital-parts are 1.8 V. First measurement results meet most of the Bluetooth specification v2.Q+EDR and show the suitability of the presented single-chip concept.
Keywords :
Bluetooth; CMOS digital integrated circuits; multimedia communication; system-on-chip; 0.18 mum; 1.5 MHz; 1.8 V; 65 mA; CMOS technology; direct up conversion architecture; dual bus architecture; enhanced data rate; multi chip package; multimedia applications; receiver; sub-band codec; system on chip; transmitter; v2.0+EDR Bluetooth SOC architecture; Baseband; Bluetooth; CMOS technology; Codecs; Data communication; Flash memory; Multimedia systems; System buses; System-on-a-chip; Transmitters;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2006.1649661
Filename :
1649661
Link To Document :
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