Clock suppression techniques for synchronous circuits

A clock suppression based technique that takes advantage of the higher abstraction level provided by synchronous design techniques to improve logic simulation performance was given by the authors (see Proc. IEEE Int. Conf. on Comput. Aided Des. Integr. Circuit Syst., pp.62-65, 1990). Here, the authors elaborate on those techniques and present extensions that can offer an average performance increase of over 5× and a peak performance increase of over 10× that of a conventional logic simulator. The viability of the approach is shown by presenting results from switch-level simulations of large industrial examples. It is shown that because clock suppression based techniques are CPU-bound, they can take advantage of the recent explosive growth of CPU performance