Title :
Fast CMOS ECL receivers with 100-mV worst-case sensitivity
Author :
Chappell, Barbara A. ; Chappell, Terry I. ; Schuster, Stanely E. ; Segmuller, Hermann M. ; Allan, James W. ; Franch, Robert L. ; Restle, Phillip J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process.<>
Keywords :
CMOS integrated circuits; compensation; differential amplifiers; emitter-coupled logic; feedback; integrated logic circuits; integrated memory circuits; receivers; 1 micron; 100 mV; 100-mV worst-case sensitivity; 5 V; 5 V one micron technology; CMOS ECL receivers; CMOS inverter; SRAM; common-mode parameter variations; differential-amplifier stage; emitter-coupled logic; feedback compensation; interleaved layout; logic interfacing; onchip CMOS levels; small-signal interfaces; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Delay; Differential amplifiers; Feedback; Inverters; Power supplies; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
