High-quality stacked CMOS inverter

Author

Zingg, R.P. ; Höfflinger, B. ; Neudeck, Gerold W.

Author_Institution

Inst. for Microelectron., Stuttgart, West Germany

Volume

11

Issue

1

fYear

1990

Firstpage

9

Lastpage

11

Abstract

A stacked CMOS technology with enhanced device performance and small geometries is discussed. Surface-channel mobilities were measured to be 700 cm/sup 2//V-s for bulk n-channel devices and 165 cm/sup 2//V-s for the top PMOS transistors. Excellent subthreshold slope of 100 mV/decade and leakage currents below 150-fA/ mu m channel width were measured for both device types. The low-impurity crystalline silicon film on top of the bulk devices was produced by local epitaxial overgrowth, an important alternative to recrystallized silicon films for three-dimensional CMOS circuits. The structure is planarized and requires only size masks with reduced processing time.<>

Keywords

CMOS integrated circuits; carrier mobility; integrated circuit technology; leakage currents; logic gates; PMOS transistors; Si recrystallized films; bulk n-channel devices; channel width; decade; device performance; leakage currents; local epitaxial overgrowth; low-impurity crystalline silicon film; planarized structure; processing time; size masks; small geometries; stacked CMOS inverter; subthreshold slope; surface channel mobilities; three-dimensional CMOS circuits; CMOS technology; Circuits; Crystallization; Current measurement; Geometry; Inverters; Leakage current; MOSFETs; Semiconductor films; Silicon;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.46914

Filename

46914