DocumentCode :
1011647
Title :
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
Author :
Shang, Li ; Peh, Li-Shiuan ; Jha, Niraj K.
Volume :
1
Issue :
1
fYear :
2002
Firstpage :
6
Lastpage :
6
Abstract :
Power consumption is a key issue in highperformanceinterconnection network design. Communicationlinks, already a aignificant consumer of power now,will take up an ever larger portion of the power budgetas demand for network bandwidth increases. In this paper,we motivate the use of dynamic voltage scaling (DVS)for links, where the frequency and voltage of links are dynamicallyadjusted to minimize power consumption. Wepropose a history-based DYS algorithm that jjlidiciously adjustsDVS poIicies based on past link utilization. Despitevery conservative assumptions about DVS link characteristics,our approach realizes up to 4.5X power savings (3.2Xaverage), with just an average 27.4% Iatency increase and2.5% throughput reduction. To the best of our knowledge,this is the first study that targets dynamic power optimizationof interconnection networks.
Keywords :
Dynamic voltage scaling; interconnection network; power optimization.; Clocks; Dynamic voltage scaling; Frequency synthesizers; Multiprocessor interconnection networks; Regulators; Dynamic voltage scaling; interconnection network; power optimization.;
fLanguage :
English
Journal_Title :
Computer Architecture Letters
Publisher :
ieee
ISSN :
1556-6056
Type :
jour
DOI :
10.1109/L-CA.2002.10
Filename :
1650108
Link To Document :
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