Title :
Design implementation of ATM switch with input priority and distributed output buffers
Author_Institution :
Dept. of Electron. & Comput. Eng., Univ. of Pertanian Malaysia, Serdang
fDate :
9/28/1995 12:00:00 AM
Abstract :
A switch architecture for ATM is described which uses a simple priority module to resolve input contention and a distributed design to permit transfer of input cells to the first free output buffer. The switch has been synthesised using VHDL software and a target generic library and can operate at speeds >400 Mbit/s
Keywords :
asynchronous transfer mode; electronic switching systems; hardware description languages; 400 Mbit/s; ATM switch; VHDL software; architecture; design; distributed output buffers; input priority module; target generic library;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19951195
