Title :
Fast two´s complement VLSI adder design
Author :
Dobson, J.M. ; Blair, G.M.
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
9/28/1995 12:00:00 AM
Abstract :
The design by Srinivas and Parhi (1992) which used redundant-number adders for fast two´s complement addition is re-examined. The underlying mechanism is revealed and improvements are presented which lead to a static-logic binary-tree carry generator to support high speed adder implementations with a delay of [log2(N)]+2 gates
Keywords :
VLSI; adders; integrated logic circuits; logic design; redundant number systems; VLSI design; delay; fast two complement addition; high speed adder; redundant-number system; static-logic binary-tree carry generator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19951200
