DocumentCode :
1012583
Title :
Integer multipliers with overflow detection
Author :
Gok, Mustafa ; Schulte, Michael J. ; Arnold, Mark G.
Author_Institution :
Cukorova Univ., Adana
Volume :
55
Issue :
8
fYear :
2006
Firstpage :
1062
Lastpage :
1066
Abstract :
This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay
Keywords :
digital arithmetic; multiplying circuits; array integer multiplier design; computer arithmetic; overflow detection circuit; overflow detection technique; tree integer multiplier design; Arithmetic; Circuit testing; Concurrent computing; Delay estimation; Java; Logic arrays; Logic circuits; Microprocessors; Senior members; Virtual machining; Computer arithmetic; combinational logic; high-speed arithmetic algorithms; multiplication.; overflow detection;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2006.126
Filename :
1650203
Link To Document :
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