Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer combinational circuits. The tolerance estimates generated by the tool match SPICE-generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT), which uses the tolerance estimates generated by ASERTA. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation-based optimization methodology, the sizes, supply voltages, and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added capacitive loads. Experiments on ISCAS´85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our approach has a significantly better energy-delay-reliability tradeoff compared with others.