Area efficient VLSI architectures for Huffman coding

In this paper, we present simple and area efficient VLSI architectures for Huffman coding, an industrial standard proposed by MPEG, JPEG, and others. We use a memory of size O(n log n) bits to store a Huffman code tree, where a is the number of symbols. This storage scheme supports real-time encoding and decoding. In addition, few simple arithmetic operations are performed on the chip for encoding and decoding. Based on our scheme, we show a design for I-bit symbols. The proposed design requires 256×9 and 64×18-bit memory modules to process 8-bit symbols. The chip occupies a silicon area of 3.5×3.5 mm² using 1.2 micron CMOSN standard library cells. Compared with a known parallel implementation which requires up to 65536 PE´s, the proposed architecture leads to a single PE design. It requires significantly less area than the known single PE design. Different Huffman codes can be stored by changing the contents of the memory, without changing the design