DocumentCode :
1013270
Title :
Circuit implementation of a peak detector neural network
Author :
Dempsey, G.L. ; Mcvey, E.S.
Author_Institution :
Dept. of Electr. Eng. & Technol., Bradley Univ., Peoria, IL, USA
Volume :
40
Issue :
9
fYear :
1993
fDate :
9/1/1993 12:00:00 AM
Firstpage :
585
Lastpage :
591
Abstract :
Peak detection is a basic data analysis problem which is essential in a large number of applications. In applications such as image processing, the large computational effort to locate peaks may prohibit operation in real-time. A Hopfield neural network is proposed for the peak detector to solve the real-time problem. Analytical expressions are derived for input separation, neuron gain, and restrictions on initial conditions. Hardware limitations are discussed and a modified circuit model is suggested for the Hopfield neuron. Solution time under thirty microseconds is obtainable with general purpose operational amplifiers independent of the number of inputs. Results obtained from a twenty-five neuron hardware implementation of the network lend credence to the theoretical results
Keywords :
Hopfield neural nets; analogue processing circuits; image processing equipment; operational amplifiers; Hopfield neural network; analogue circuits; circuit model; computational effort; data analysis problem; hardware limitations; image processing; input separation; neuron gain; operational amplifiers; peak detector neural network; real-time problem; Detectors; Differential equations; Hardware; Image processing; Logic circuits; Neural networks; Neurons; Operational amplifiers; Space technology; Voltage;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.257342
Filename :
257342
Link To Document :
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