Operation of a VBL memory write gate

A write gate for the VBL memory was designed and fabricated on an as-grown garnet wafer supporting 5 μm bubbles. Pictures of the transient stripe during the write operation were taken showing the effectiveness of the gate design in controlling the stripe head motion and the generation of the VBL´s in the head, There are two regions of operational margin for the expanding current, one is between 23 and 48 mA, with 500 to 700 nsec pulse width, the other is between 68 and 92 mA. with 300 to 700 nsec pulse width. The operation of the write gate is independent of the in-plane field.