Title :
A reduced-area scheme for carry-select adders
Author_Institution :
Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
fDate :
10/1/1993 12:00:00 AM
Abstract :
The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the cases. The proposed carry-select scheme is assessed relative to carry-ripple, classical carry-select, and carry-skip adders. The analytic evaluation is done with respect to the gate-count model for area and gate-delay units for time
Keywords :
adders; logic circuits; logic design; analytic evaluation; area-efficient; carry-chain evaluations; carry-ripple; carry-select adders; carry-skip adders; classical carry-select; conditional-sum adders; gate-count; gate-delay; parallel-prefix adders; reduced-area; Computer science; Costs; Counting circuits; Delay; Logic; Microprocessors; Pipelines; Signal processing; Time factors; Wires;
Journal_Title :
Computers, IEEE Transactions on
