DocumentCode :
1013524
Title :
Creating disjoint paths in Gamma interconnection networks
Author :
Tzeng, Nian-Feng ; Chuang, Po-Jen ; Wu, Chwan-Hwa
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Volume :
42
Issue :
10
fYear :
1993
fDate :
10/1/1993 12:00:00 AM
Firstpage :
1247
Lastpage :
1252
Abstract :
The Gamma interconnection network (GIN) is composed of 3×3 basic building blocks, with interconnecting patterns between stages following the plus-minus-2i functions. The authors consider modifications to the GIN by altering the interconnecting patterns between stages so as to achieve high terminal reliability between any source-destination pair, resulting in the reliable GIN (REGIN). A type of REGIN´s ensures totally disjoint paths in existence from any source to any destination, thereby capable of tolerating an arbitrary single fault. If several building blocks (i.e., 3×3 switches) are fabricated in one chip with very large scale integrated (VLSI) technology, the layout area and the pin count are less for the REGIN than for its GIN counterpart as a result of the change in the interconnecting patterns, giving rise to potential cost reduction. The terminal reliability of the REGIN is derived and compared with that of a compatible GIN. In addition, the performance of the REGIN is evaluated using simulation
Keywords :
fault tolerant computing; multiprocessor interconnection networks; network routing; performance evaluation; Gamma interconnection networks; VLSI; disjoint paths; high terminal reliability; layout area; performance; pin count; simulation; source-destination pair; Computer network reliability; Costs; Fault tolerance; Hardware; Intelligent networks; Multiprocessing systems; Multiprocessor interconnection networks; Routing; Switches; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.257710
Filename :
257710
Link To Document :
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