Abstract :
Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in digital communication and storage systems. Among the decoding algorithms of RS codes, the recently developed Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while has a polynomial complexity. One of the major steps of the KV algorithm is the factorization. Each iteration of the factorization mainly consists of root computations over finite fields and polynomial updating. To speed up the factorization step, a fast factorization architecture has been proposed to circumvent the exhaustive-search-based root computation from the second iteration level by using a root-order prediction scheme. Based on this scheme, a partial parallel factorization architecture was proposed to combine the polynomial updating in adjacent iteration levels. However, in both of these architectures, the root computation in the first iteration level is still carried out by exhaustive search, which accounts for a significant part of the overall factorization latency. In this paper, a novel iterative prediction scheme is proposed for the root computation in the first iteration level. The proposed scheme can substantially reduce the latency of the factorization, while only incurs negligible area overhead. Applying this scheme to a (255, 239) RS code, speedups of 36% and 46% can be achieved over the fast factorization and partial parallel factorization architectures, respectively.
Keywords :
Reed-Solomon codes; error correction codes; iterative decoding; polynomials; prediction theory; Koetter-Vardy soft-decision decoding algorithm; Reed-Solomon codes; VLSI architecture; digital communication; error-correcting codes; exhaustive-search-based root computation; fast factorization architecture; finite fields; iteration level; iterative prediction scheme; partial parallel factorization architecture; polynomial updating; root-order prediction scheme; soft-decision Reed-Solomon decoding; storage systems; Computer architecture; Delay; Digital communication; Error correction codes; Galois fields; Interpolation; Iterative decoding; Polynomials; Prediction algorithms; Very large scale integration; Factorization; Koetter–Vardy (KV) algorithm; Reed–Solomon (RS) code; VLSI architecture; iterative prediction; soft-decision decoding;