DocumentCode
1014246
Title
A Combined Circuit for Multiplication and Inversion in
Author
Kobayashi, Katsuki ; Takagi, Naofumi
Author_Institution
Dept. of Inf. Eng., Nagoya Univ., Nagoya
Volume
55
Issue
11
fYear
2008
Firstpage
1144
Lastpage
1148
Abstract
A combined circuit for multiplication and inversion in GF(2m) is proposed. In order to develop a combined circuit, we start with combining the most significant bit first multiplication algorithm and the modified extended Euclid´s algorithm by focusing on the similarities between them. Since almost all hardware components of the circuits are shared by multiplication and inversion, the combined circuit can be implemented with significantly smaller hardware than that necessary to implement both multiplication and inversion separately. By logic synthesis, the area of the proposed circuit is estimated to be approximately over 15% smaller than that of previously proposed combined multiplication/division circuits.
Keywords
algorithm theory; formal logic; Euclid´s algorithm; bit first multiplication algorithm; combined multiplication/division circuit; inversion; logic synthesis; Galois field; inversion; multiplication;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2008.2003347
Filename
4694007
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