Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET´s

The threshold voltage, V_th, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V_th roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, ΔV_th is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V _th design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V_th design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained