Future WSI technology: stacked monolithic WSI

Describes a methodology for stacking chips vertically and interconnecting them through the chips to achieve a three-dimensional (3D) circuit. This methodology involves the integration of two technologies: indium bump interconnect technology, historically used to fabricate hybrid focal plane arrays, and the precision thinning of bonded silicon wafers by a process called Acuthin. Substantial improvements in computing density, power dissipation, and signal propagation time can be realized. This paper describes some of the techniques and benefits of this 3D interconnect methodology