Future WSI technology: stacked monolithic WSI

Author

Williams, Ronald ; Marsh, Ogden

Author_Institution

Technol. Center, Hughes Aircraft Co., Carlsbad, CA, USA

Volume

16

Issue

7

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

610

Lastpage

614

Abstract

Describes a methodology for stacking chips vertically and interconnecting them through the chips to achieve a three-dimensional (3D) circuit. This methodology involves the integration of two technologies: indium bump interconnect technology, historically used to fabricate hybrid focal plane arrays, and the precision thinning of bonded silicon wafers by a process called Acuthin. Substantial improvements in computing density, power dissipation, and signal propagation time can be realized. This paper describes some of the techniques and benefits of this 3D interconnect methodology

Keywords

VLSI; integrated circuit technology; metallisation; monolithic integrated circuits; 3D interconnect methodology; Acuthin; WSI technology; computing density; indium bump interconnect technology; power dissipation; precision thinning; signal propagation time; stacked monolithic WSI; Detectors; Indium; Integrated circuit interconnections; Power system interconnection; Sensor arrays; Silicon; Stacking; Thermal stresses; Wafer bonding; Wafer scale integration;

fLanguage

English

Journal_Title

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

0148-6411

Type

jour

DOI

10.1109/33.257874

Filename

257874