Title :
Demonstration of Metal-Gated Low Vt n-MOSFETs Using a Poly-Si/TaN/Dy2O3/SiON Gate Stack With a Scaled EOT Value
Author :
Yu, H.Y. ; Singanamalla, R. ; Ragnarsson, L. Å ; Chang, V.S. ; Cho, H.J. ; Mitsuhashi, R. ; Adelmann, C. ; Van Elshocht, S. ; Lehnen, P. ; Chang, S.Z. ; Yin, K.M. ; Schram, T. ; Kubicek, S. ; De Gendt, S. ; Absil, P. ; De Meyer, K. ; Biesemans, S.
Author_Institution :
Interuniv. Microelectron. Center, Leuven
fDate :
7/1/2007 12:00:00 AM
Abstract :
In this letter, we report that by using a thin dysprosium oxide (Dy2O3)cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (Vt) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy2O3 cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.
Keywords :
MOSFET; carrier mobility; dysprosium compounds; silicon; silicon compounds; tantalum compounds; transmission electron microscopy; EOT value; Si-TaN-Dy2O3-SiON; Si-TaN-Dy2O3-SiON - Interface; equivalent oxide thickness; gate leakage; gate stack; host dielectrics; long channel devices mobility; minor degradation; n-MOSFET; threshold voltage; time-zero-break-down characteristics; transmission electron microscopy measurement; CMOS process; CMOS technology; Degradation; Dielectric devices; Fabrication; Gate leakage; MOSFET circuits; Microelectronics; Semiconductor device manufacture; Threshold voltage; DySiON; MIPS; SiON; TaN; dysprosium oxide $(hbox{Dy}_{2} hbox{O}_{3})$; n-MOSFETs;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2007.900308
