• DocumentCode
    1014943
  • Title

    Achieving Programming Model Abstractions for Reconfigurable Computing

  • Author

    Andrews, David ; Sass, Ron ; Anderson, Erik ; Agron, Jason ; Peck, Wesley ; Stevens, Jim ; Baijot, Fabrice ; Komp, Ed

  • Author_Institution
    Kansas Univ., Lawrence
  • Volume
    16
  • Issue
    1
  • fYear
    2008
  • Firstpage
    34
  • Lastpage
    44
  • Abstract
    This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.
  • Keywords
    field programmable gate arrays; high level languages; multiprocessing systems; reconfigurable architectures; POSIX threads; application threads; computer processing unit; field-programmable gate-array; hardware thread interface; high level languages; hthreads system; programming model abstractions; reconfigurable computing; unified multiprocessor architecture; Application software; Central Processing Unit; Computational modeling; Computer architecture; Computer languages; Field programmable gate arrays; Hardware; Middleware; Operating systems; Field-programmable gate arrays (FPGAs); operating systems; programming models; reconfigurable computing;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2007.912106
  • Filename
    4407532