Author :
Jiang, Rong ; Chang, Yi-Hao ; Chen, Charlie Chung-Ping
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
This paper presents an efficient, simple, hierarchical, and sparse three-dimensional capacitance extraction algorithm, i.e., ICCAP. Most previous capacitance extraction algorithms, such as FastCap and HiCap, introduce intermediate variables to facilitate the hierarchical potential calculation, but still preserve the basic panels as basis. In this paper, we discover that those intermediate variables are a fundamentally much better basis than leaf panels. As a result, we are able to explicitly construct the sparse potential coefficient matrix and solve it with linear memory and linear run time in comparison with the most recent hierarchical O(nlogn) approach in PHiCap. Furthermore, the explicit sparse formulation of a potential matrix not only enables the usage of preconditioned Krylov subspace iterative methods, but also the reordering technique. A new reordering technique, i.e., level-oriented reordering (LOR), is proposed to further reduce over 20% of memory consumption and run time compared with no reordering techniques applied. In fact, LOR is even better than the state-of-the-art minimum degree reordering and more efficient. Without complicated orthonormalization matrix computation, ICCAP is very simple, efficient, and accurate. Experimental results demonstrate the superior run time and memory consumption over previous approaches while achieving similar accuracy.
Keywords :
boundary-elements methods; capacitance measurement; sparse matrices; 3D BEM capacitance extraction; ICCAP; boundary element method; linear memory; linear run time; linear time sparsification; preconditioned Krylov subspace iterative methods; reordering algorithm; sparse potential coefficient matrix; Acceleration; Frequency; Iterative algorithms; Iterative methods; Linear systems; Matrix decomposition; Packaging; Parasitic capacitance; Sparse matrices; Very large scale integration; Basis; boundary-element method (BEM); capacitance extraction; hierarchical algorithm; interconnect; interconnect modeling; parasitic extraction; reordering;